Digital communication buses operating at high frequencies distort the signals in a manner that leads to inter-symbol interference and reflections. One method for reducing this interference and reflections involves the use of a decision feedback equalizer (DFE). The DFE generates a feedback signal based on the values of the previously received bits. The feedback signal is combined with the signal for the current bit to compensate for distortions introduced by inter-symbol interference caused by the previous bits or reflections caused by discontinuities in the characteristic impedance of the transmission path. The DFE can be viewed as a finite impulse response filter (FIR) having one tap for each previously received bit that is to be incorporated in the feedback signal. Each weight of the FIR is set by setting the gain of an amplifier whose input is a signal representing the corresponding previous bit.
In general, the DFE is imbedded in a custom integrated circuit (ASIC) that receives a data signal and generates an output data signal that is corrected for the inter-symbol interference and/or reflected signal components. The amplifiers that implement the FIR are “buried” in the ASIC in a manner that makes directly observing the gain of each amplifier by measuring the output of that amplifier difficult. However, the amplifiers in the ASIC must be characterized after the design is actually fabricated to determine the actual gains of the amplifiers as a function of the internal signals that specify the target gain for each amplifier. For example, in some embodiments there is a digital word that sets the gain of a corresponding amplifier by converting the digital value to an analog value that is coupled to the analog gain input of the amplifier. The amplifier gain as a function of the control word value must be measured to qualify the ASIC design and/or test parts on a production line. This testing procedure presents significant challenges for the test engineers who cannot directly observe the gain of each amplifier.